| CPC H10D 62/151 (2025.01) [H10D 30/6213 (2025.01); H10D 62/8325 (2025.01); H10D 84/834 (2025.01)] | 20 Claims |
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1. A semiconductor device, comprising:
first channels of a first transistor type on a first region of a substrate, the substrate including the first region and a second region, the first channels being spaced apart from each other in a vertical direction perpendicular to an upper surface of the substrate, and each of the first channels extending in a first direction parallel to the upper surface of the substrate;
second channels of a second transistor type on the second region of the substrate, the second transistor type being different than the first transistor type, the second channels being spaced apart from each other on the second region of the substrate in the vertical direction, each of the second channels extending in the first direction;
a first gate structure extending in a second direction on the first region of the substrate to cover at least a portion of a surface of each of the first channels, the second direction being parallel to the upper surface of the substrate and crossing the first direction;
a second gate structure extending in the second direction on the second region of the substrate to cover at least a portion of a surface of each of the second channels;
a first source/drain layer at each of opposite sides of the first gate structure in the first direction, the first source/drain layer contacting the first channels in the first direction;
a second source/drain layer at each of opposite sides of the second gate structure in the first direction, the second source/drain layer contacting the second channels in the first direction; and
an inner spacer between the second channels, the inner spacer contacting the second source/drain layer and the second gate structure,
wherein a sidewall of the second source/drain layer contacting the inner spacer has a protrusion protruding toward the second gate structure.
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