| CPC H10D 30/6735 (2025.01) [H10D 30/6757 (2025.01); H10D 62/151 (2025.01)] | 20 Claims |
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1. A semiconductor device comprising:
an active pattern including a lower pattern and a plurality of sheet patterns on the lower pattern and spaced apart from the lower pattern;
a gate structure on the lower pattern and surrounding the plurality of sheet patterns;
a source/drain pattern on at least one side of the gate structure and filling a source/drain recess; and
a source/drain contact on the source/drain pattern,
wherein the source/drain pattern includes a first semiconductor pattern extending along the source/drain recess and contacting the lower pattern, a second semiconductor pattern on the first semiconductor pattern, a third semiconductor pattern on the second semiconductor pattern, and a fourth semiconductor pattern on the third semiconductor pattern and filing the source/drain recess,
a side surface of the third semiconductor pattern includes a planar portion,
a lowermost surface of the second semiconductor pattern includes a planar portion,
a lowermost surface of the third semiconductor pattern includes a planar portion,
a length of the planar portion of the lowermost surface of the second semiconductor pattern is smaller than a length of the planar portion of the lowermost surface of the third semiconductor pattern, and
a thickness of the second semiconductor pattern on the lowermost surface of the third semiconductor pattern is different from a thickness of the second semiconductor pattern on the planar portion of the side surface of the third semiconductor pattern.
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