| CPC H10D 30/6729 (2025.01) [H10D 30/6717 (2025.01); H10D 30/6728 (2025.01); H10D 30/6758 (2025.01); H10K 59/1213 (2023.02)] | 16 Claims |
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1. A vertical inverter comprising:
an insulation substrate;
a first thin film transistor disposed on the insulation substrate, wherein the first thin film transistor comprises a first active layer comprising a first channel region and N-type doped regions disposed on opposite sides of the first channel region;
a second thin film transistor disposed on a side of the first thin film transistor away from the insulation substrate, wherein the second thin film transistor comprises a second active layer, a source, and a drain, wherein the second active layer comprises a second channel region and P-type doped regions disposed on opposite sides of the second channel region, wherein one of the P-type doped regions in the second active layer is electrically connected to a corresponding one of the N-type doped regions in the first active layer, and wherein one of the source and the drain is electrically connected to one of the P-type doped regions in the second active layer and one of the N-type doped regions in the first active layer;
a first insulation layer disposed between the first active layer and the second active layer, wherein the first thin film transistor further comprises at least one auxiliary electrode disposed between the first insulation layer and the second active layer, and the at least one auxiliary electrode passes through the first insulation layer and contacts a corresponding one of the N-type doped regions;
a second insulation layer disposed between the at least one auxiliary electrode and the second active layer; and
a third insulation layer disposed on a side of the second active layer away from the second insulation layer,
wherein the source and the drain are disposed on a side of the third insulation layer away from the second insulation layer, and
wherein one of the source and the drain sequentially passes through the third insulation layer, a corresponding one of the P-type doped region, and the second insulation layer, and the source and the drain contact the at least one auxiliary electrode and one of the P-type doped regions, respectively.
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