US 12,289,906 B2
Vertical power devices fabricated using implanted methods
Daniel Jenner Lichtenwalner, Raleigh, NC (US); Sei-Hyung Ryu, Cary, NC (US); and Arman Ur Rashid, Durham, NC (US)
Assigned to Wolfspeed, Inc., Durham, NC (US)
Filed by Wolfspeed, Inc., Durham, NC (US)
Filed on Jan. 31, 2024, as Appl. No. 18/428,533.
Application 18/428,533 is a continuation of application No. 17/482,019, filed on Sep. 22, 2021, granted, now 11,894,455, issued on Feb. 6, 2024.
Prior Publication US 2024/0178314 A1, May 30, 2024
Int. Cl. H01L 29/78 (2006.01); H01L 29/66 (2006.01); H01L 29/808 (2006.01); H01L 29/861 (2006.01); H10D 8/00 (2025.01); H10D 30/01 (2025.01); H10D 30/66 (2025.01); H10D 30/83 (2025.01)
CPC H10D 30/66 (2025.01) [H10D 8/00 (2025.01); H10D 30/0291 (2025.01); H10D 30/831 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A vertical semiconductor device comprising:
a substrate;
a drift region over the substrate;
an upper region on the drift region, a top surface over the upper region and being substantially planar; and
a series of implants of a second dopant in the upper region, such that each implant of the series of implants is located at a different depth below the top surface, the series of implants forming at least two gate regions;
wherein:
the substrate and the drift region are doped with a first dopant of a first polarity;
the second dopant has a second polarity opposite that of the first polarity;
at least a portion of a channel region is provided between the at least two gate regions; and
a conducting gap is defined within the channel region and between opposing sidewalls of the at least two gate regions.