CPC H10D 30/658 (2025.01) [H01L 21/76 (2013.01); H01L 21/762 (2013.01); H10D 30/0289 (2025.01); H10D 30/603 (2025.01); H10D 62/116 (2025.01); H10D 64/516 (2025.01); H10D 64/518 (2025.01)] | 20 Claims |
1. A method for fabricating a semiconductor structure, comprising:
forming an isolation trench in a substrate;
forming a silicon oxide trench fill layer to at least fill the isolation trench in the substrate, the silicon oxide trench fill layer comprising a first portion in the isolation trench;
removing a second portion of the first portion of the silicon oxide trench fill layer in the isolation trench, without exposing a bottom of the isolation trench in the substrate;
forming a first well region in the substrate that includes the isolation trench, the first well region having a first conductivity type and wherein the first portion of the silicon oxide trench fill layer contacts the first well region; and
forming a gate structure over the substrate, wherein the gate structure contacts the first well region of the substrate and fills an empty portion of the isolation trench in the first well region of the substrate created by removing the second portion.
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