US 12,289,904 B2
Nitride-based semiconductor device and method for manufacturing the same
Yi-Lun Chou, Suzhou (CN); Shuang Gao, Suzhou (CN); and Chuangang Li, Suzhou (CN)
Assigned to INNOSCIENCE (SUZHOU) TECHNOLOGY CO., LTD., Suzhou (CN)
Filed by INNOSCIENCE (SUZHOU) TECHNOLOGY CO., LTD., Suzhou (CN)
Filed on Feb. 14, 2022, as Appl. No. 17/671,558.
Application 17/671,558 is a continuation of application No. 17/623,259, previously published as PCT/CN2021/129628, filed on Nov. 9, 2021.
Prior Publication US 2023/0147426 A1, May 11, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H10D 30/47 (2025.01); H01L 21/02 (2006.01); H01L 21/306 (2006.01); H01L 21/76 (2006.01); H10D 30/01 (2025.01); H10D 62/10 (2025.01); H10D 62/824 (2025.01); H10D 62/85 (2025.01)
CPC H10D 30/475 (2025.01) [H01L 21/02241 (2013.01); H01L 21/0254 (2013.01); H01L 21/30612 (2013.01); H01L 21/7605 (2013.01); H10D 30/015 (2025.01); H10D 30/4755 (2025.01); H10D 30/477 (2025.01); H10D 62/113 (2025.01); H10D 62/824 (2025.01); H10D 62/8503 (2025.01)] 15 Claims
OG exemplary drawing
 
1. A nitride-based semiconductor device, comprising:
a first nitride-based semiconductor layer doped to a first conductivity type;
a second nitride-based semiconductor layer disposed over the first nitride-based semiconductor layer;
a lattice layer disposed between the first and second nitride-based semiconductor layers and doped to the first conductivity type, wherein the lattice layer comprises a plurality of first III-V layers and a plurality of second III-V layers alternatively stacked, each of the first III-V layers has a high resistivity region and a current aperture enclosed by the high resistivity region, the high resistivity region comprises more metal oxides than the current aperture so as to achieve a resistivity higher than that of the current aperture, wherein at least two of the current apertures have different dimensions such that at least two of interfaces formed between the high resistivity regions and the current apertures misalign with each other;
a third nitride-based semiconductor layer disposed over the second nitride-based semiconductor layer;
a first source electrode and a second source electrode disposed over the third nitride-based semiconductor layer; and
a gate electrode disposed over the third nitride-based semiconductor layer and between the first source electrode and the second source electrode, wherein the gate electrode aligns with the current aperture.