US 12,289,892 B2
Memory device structure and manufacturing method thereof
Bo-Feng Young, Taipei (TW); Sai-Hooi Yeong, Hsinchu County (TW); Yu-Ming Lin, Hsinchu (TW); Chao-I Wu, Hsinchu County (TW); and Mauricio Manfrini, Hsinchu County (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Feb. 8, 2021, as Appl. No. 17/169,554.
Claims priority of provisional application 63/045,194, filed on Jun. 29, 2020.
Prior Publication US 2021/0408013 A1, Dec. 30, 2021
Int. Cl. G11C 11/16 (2006.01); H10B 51/30 (2023.01); H10B 61/00 (2023.01); H10D 30/01 (2025.01); H10D 30/69 (2025.01); H10N 50/01 (2023.01); H10N 50/10 (2023.01); H10N 50/80 (2023.01)
CPC H10B 51/30 (2023.02) [G11C 11/161 (2013.01); H10B 61/22 (2023.02); H10D 30/0415 (2025.01); H10D 30/701 (2025.01); H10N 50/01 (2023.02); H10N 50/10 (2023.02); H10N 50/80 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A memory device, comprising:
a substrate, having a semiconductor device and a dielectric structure disposed on the semiconductor device;
a transistor, disposed over the dielectric structure and electrically coupled with the semiconductor device, comprising:
a gate disposed over the dielectric structure;
source and drain regions disposed over the dielectric structure;
a channel layer located between the source and drain regions; and
a stack of a gate dielectric layer and a first ferroelectric layer disposed between the gate and the channel layer, wherein the stack of the gate dielectric layer and the first ferroelectric layer conformally covers a top surface and sidewalls of the gate, wherein the first ferroelectric layer is in direct contact with the top surface and the sidewalls of the gate; and
a memory cell, disposed over the transistor and electrically connected to one of the source and drain regions of the transistor, wherein the memory cell includes a ferromagnetic layer or a second ferroelectric layer.