| CPC H10B 51/20 (2023.02) [H10B 51/30 (2023.02)] | 20 Claims |

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1. A ferroelectric memory device, comprising:
an alternating stack of insulating layers and electrically conductive layers;
a memory opening extending vertically through the alternating stack and including laterally-protruding portions at levels of the electrically conductive layers; and
a memory opening fill structure located in the memory opening and comprising a vertical semiconductor channel and a vertical stack of discrete ferroelectric memory structures located in the laterally-protruding portions of the memory opening,
wherein each of the ferroelectric memory structures comprises a crystalline ferroelectric material portion and a crystalline template material portion located between a respective electrically conductive layer of the electrically conductive layers and the crystalline ferroelectric material portion.
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