US 12,289,883 B2
One time programming memory cell with fin field-effect transistor using physically unclonable function technology
Lun-Chun Chen, Hsinchu County (TW); and Ping-Lung Ho, Hsinchu County (TW)
Assigned to EMEMORY TECHNOLOGY INC., Hsin-Chu (TW)
Filed by eMemory Technology Inc., Hsinchu (TW)
Filed on Jul. 10, 2023, as Appl. No. 18/219,864.
Claims priority of provisional application 63/388,258, filed on Jul. 12, 2022.
Prior Publication US 2024/0021256 A1, Jan. 18, 2024
Int. Cl. G11C 5/02 (2006.01); G11C 16/24 (2006.01); G11C 16/26 (2006.01); G11C 17/16 (2006.01); H01L 23/00 (2006.01); H02H 9/02 (2006.01); H10B 20/25 (2023.01)
CPC H10B 20/25 (2023.02) [G11C 16/24 (2013.01); G11C 16/26 (2013.01); G11C 17/16 (2013.01); H01L 23/576 (2013.01); H02H 9/02 (2013.01)] 36 Claims
OG exemplary drawing
 
1. A one time programming (OTP) memory cell using a physically unclonable function technology, the OTP memory cell comprising:
a first fin;
a second fin;
a first gate structure comprising a first gate dielectric layer, a second gate dielectric layer and a first gate layer, wherein a top surface and two lateral surfaces of a central region of the first fin are covered by the first gate dielectric layer, a top surface and two lateral surfaces of a central region of the second fin are covered by the second gate dielectric layer, the first gate dielectric layer and the second gate dielectric layer are covered by the first gate layer, and the first gate layer is connected with an antifuse control line;
a first drain/source contact layer electrically connected with a first terminal of the first fin and a first terminal of the second fin;
a second drain/source contact layer electrically connected with a second terminal of the second fin, wherein the second drain/source contact layer is not electrically connected with a second terminal of the first fin;
a first transistor comprising a first drain/source terminal, a gate terminal and a second drain/source terminal, wherein the second drain/source terminal of the first transistor is connected with the first drain/source contact layer; and
a second transistor comprising a first drain/source terminal, a gate terminal and a second drain/source terminal, wherein the first drain/source terminal of the second transistor is connected with the second drain/source contact layer.