| CPC H04W 72/53 (2023.01) [H04W 4/46 (2018.02); H04W 72/0453 (2013.01); H04W 72/56 (2023.01); H04W 76/11 (2018.02)] | 12 Claims |

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12. An electronic apparatus, comprising a memory and a processor, wherein the memory is configured to store a computer program, and the processor is configured to execute the computer program to perform steps comprising:
transmitting, by a terminal, request information to a base station, the request information comprising: 5G quality of service indication (5QI), quality of service flow identity (QFI), packet delay budget (PDB), priority, packet error rate (PER), and guaranteed flow bit rate (GFBR);
receiving, by the terminal, configuration information about a sidelink bandwidth part (BWP);
performing, by the terminal, sidelink data transmission according to the received configuration information about the sidelink BWP;
transmitting, by the terminal, a scheduling request (SR) for requesting a sidelink resource; and
before transmitting, by the terminal, the SR for requesting the sidelink resource, receiving, by the terminal, SR configuration which is transmitted by the base station and
dedicated to requesting a sidelink communication.
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