US 12,289,550 B2
Imaging system and imaging device
Naoki Kawazu, Kanagawa (JP); Atsushi Suzuki, Kanagawa (JP); Junichiro Azami, Kanagawa (JP); and Yuichi Motohashi, Tokyo (JP)
Assigned to Sony Semiconductor Solutions Corporation, Kanagawa (JP)
Filed by Sony Semiconductor Solutions Corporation, Kanagawa (JP)
Filed on Jan. 4, 2024, as Appl. No. 18/404,153.
Application 18/404,153 is a continuation of application No. 17/062,481, filed on Oct. 2, 2020, granted, now 11,902,681.
Application 17/062,481 is a continuation of application No. 16/483,417, granted, now 11,706,538, previously published as PCT/JP2018/000819, filed on Jan. 15, 2018.
Claims priority of application No. 2017-026823 (JP), filed on Feb. 16, 2017; and application No. 2017-197509 (JP), filed on Oct. 11, 2017.
Prior Publication US 2024/0155264 A1, May 9, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H04N 25/75 (2023.01); H01L 27/146 (2006.01); H04N 5/14 (2006.01); H04N 23/65 (2023.01); H04N 25/633 (2023.01); H04N 25/772 (2023.01); H10K 39/32 (2023.01)
CPC H04N 25/75 (2023.01) [H01L 27/14612 (2013.01); H04N 5/144 (2013.01); H04N 23/65 (2023.01); H04N 25/633 (2023.01); H04N 25/772 (2023.01); H10K 39/32 (2023.02); B60R 2300/30 (2013.01); B60R 2300/80 (2013.01)] 10 Claims
OG exemplary drawing
 
1. A light detecting device comprising:
a first pixel including a first photodiode;
a second pixel including a second photodiode;
a first signal line coupled to the first pixel, the first signal line extending along a first direction;
a second signal line coupled to the second pixel, the first second line extending along the first direction;
a first analog-to-digital converter coupled to the first signal line;
a second analog-to-digital converter coupled to the second signal line;
a first control line extending along a second direction perpendicular to the first direction;
a second control line extending along the second direction;
a signal generator coupled to the first control line and the second control line;
a first transistor having a source or a drain coupled to the first signal line and a gate coupled to the first control line;
a second transistor having a source or a drain coupled to the second signal line and a gate coupled to the second control line; and
diagnosis circuitry configured to detect an error based on a digital code generated from at least one of the first analog-to-digital converter, the second analog-to-digital converter or combination thereof,
wherein the first signal line is disposed next to the second signal line.