US 12,289,384 B2
System and method for synthesis of connectivity to an interconnect in a multi-protocol system-on-chip (SoC)
K. Charles Janac, Campbell, CA (US); Vincent Thibaut, Jacou (FR); and Benoit de Lescure, Campbell, CA (US)
Assigned to ARTERIS, INC., Campbell, CA (US)
Filed by ARTERIS, INC., Campbell, CA (US)
Filed on Feb. 6, 2022, as Appl. No. 17/665,578.
Claims priority of provisional application 63/149,184, filed on Feb. 12, 2021.
Prior Publication US 2022/0263925 A1, Aug. 18, 2022
Int. Cl. G06F 15/78 (2006.01); H04L 69/08 (2022.01); H04L 69/18 (2022.01)
CPC H04L 69/08 (2013.01) [G06F 15/7825 (2013.01); H04L 69/18 (2013.01)] 7 Claims
OG exemplary drawing
 
1. A design tool comprising:
a memory for storing code; and
a processor in communication with the memory, wherein the processor executes the code that causes the design tool to:
receive information for a network-on-chip (NoC), wherein the information includes interconnect pin names and NoC packet-based protocol;
receive hardware information for an IP block that is in communication with the NoC, wherein the hardware information includes IP block pin names and IP block protocol;
generate a description for a protocol converter that handles protocol conversion between the IP block protocol and the NoC packet-based protocol, wherein the description includes NoC interface description that converts to and from the NoC packet-based protocol;
generate an initiator interface protocol conversion module when the IP block is an initiator IP block that is in communication with the NoC using a first protocol;
generate a target interface protocol conversion module for a target IP block that is in communication with the initiator IP block using the NoC, the target IP block uses a second protocol;
connect the initiator IP block using the initiator interface protocol conversion module to the NoC; and
connect the target IP block using the target interface protocol conversion module to the NoC.