US 12,289,255 B2
Systems and methods for using a packet processing pipeline circuit to extend the capabilities of rate limiter circuits
Vishwas Danivas, Santa Clara, CA (US); Murty Subba Rama Chandra Kotha, San Jose, CA (US); Tuyen Quoc, Saratoga, CA (US); Hui Peng, Cupertino, CA (US); and Kit Chiu Chu, Fremont, CA (US)
Assigned to Pensando Systems Inc., Milpitas, CA (US)
Filed by Pensando Systems Inc., Milpitas, CA (US)
Filed on Nov. 10, 2022, as Appl. No. 17/985,093.
Prior Publication US 2024/0163230 A1, May 16, 2024
Int. Cl. H04L 49/00 (2022.01); H04L 47/215 (2022.01); H04L 47/25 (2022.01); H04L 47/625 (2022.01)
CPC H04L 49/3063 (2013.01) [H04L 47/215 (2013.01); H04L 47/25 (2013.01); H04L 47/6255 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system comprising:
a first packet processing pipeline circuit that produces a plurality of network packets for a workload;
a second packet processing pipeline circuit that includes a plurality of match-action processing stages arranged as a match-action pipeline;
a logical interface (LIF) that includes a LIF queue that stores a plurality of transmission requests for transmission of the network packets for the workload;
a scheduler that schedules one of the transmission requests for processing by scheduling a transmission request (TR) packet header vector (PHV) for processing by the second packet processing pipeline circuit;
a first limiter that is implemented by the second packet processing pipeline circuit and that produces a first limiting indicator by processing the TR PHV;
a second limiter that is implemented by the second packet processing pipeline circuit and that produces a second limiting indicator by processing the TR PHV;
a rate limit calculator that produces a rate limiting decision from the first limiting indicator and the second limiting indicator; and
a rate limiter circuit that, based on the rate limiting decision, causes the scheduler to limit scheduling of TR PHVs based on the transmission requests from the workload,
wherein the first packet processing pipeline circuit produces the network packets at a rate governed by the second packet processing pipeline circuit.