US 12,289,119 B2
Low-power systematic ECC encoder with balancing bits
Idan Dekel, Suwon-si (KR); Amit Berman, Suwon-si (KR); Ariel Doubchak, Suwon-si (KR); and Yaron Shany, Suwon-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on May 3, 2023, as Appl. No. 18/142,703.
Prior Publication US 2024/0372568 A1, Nov. 7, 2024
Int. Cl. H03M 13/39 (2006.01); H03M 13/15 (2006.01); H03M 13/19 (2006.01)
CPC H03M 13/3961 (2013.01) [H03M 13/152 (2013.01); H03M 13/19 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A storage system, comprising:
a storage device configured to store a plurality of codewords;
at least one processor configured to:
obtain information bits and a target constraints vector;
place the information bits in an input vector;
set balance bits included in the input vector to zero;
encode the input vector using a systematic code to obtain a preliminary codeword;
apply a constraints matrix to the preliminary codeword to obtain a preliminary constraints vector;
apply a transition matrix to a sum of the preliminary constraints vector and the target constraints vector to determine updated balance bits;
obtain an output codeword based on the information bits and the updated balance bits; and
store the output codeword in the storage device.