US 12,289,113 B2
Delay locked loop
Chi-Hsiang Sun, Taichung (TW)
Assigned to Windbond Electronics Corp., Taichung (TW)
Filed by Winbond Electronics Corp., Taichung (TW)
Filed on May 3, 2023, as Appl. No. 18/311,251.
Claims priority of application No. 112112802 (TW), filed on Apr. 6, 2023.
Prior Publication US 2024/0340013 A1, Oct. 10, 2024
Int. Cl. H03L 7/081 (2006.01); G11C 19/00 (2006.01); H03L 7/091 (2006.01); H03K 19/20 (2006.01)
CPC H03L 7/0812 (2013.01) [G11C 19/00 (2013.01); H03L 7/091 (2013.01); H03K 19/20 (2013.01)] 13 Claims
OG exemplary drawing
 
1. A delay locked loop, comprising:
a delay line, receiving an input clock signal and a control code, and generating a delayed clock signal by delaying the input clock signal according to the control code;
a phase detector, receiving a reference clock signal and a feedback clock signal, and detecting a phase difference between the reference clock signal and the feedback clock signal to generate phase comparison information;
a controller, coupled to the delay line and the phase detector, and generating the control code and a switching signal according to the phase comparison information;
an output clock generator, coupled to the delay line and the controller, and selecting the delayed clock signal or an inverted signal of the delayed clock signal according to the switching signal to generate an output clock signal; and
a feedback circuit, coupled to the phase detector and the output clock generator, and generating the feedback clock signal according to the output clock signal.