US 12,289,112 B2
Phase-locked loop device
Shunfang Wu, Shanghai (CN); Qingxiang Dong, Shanghai (CN); and Xiaomin Si, Shanghai (CN)
Assigned to Montage LZ Technologies (Shanghai) Co., Ltd., Shanghai (CN)
Filed by Montage LZ Technologies (Shanghai) Co., Ltd., Shanghai (CN)
Filed on Nov. 2, 2023, as Appl. No. 18/501,024.
Claims priority of application No. 202211716788.7 (CN), filed on Dec. 29, 2022.
Prior Publication US 2024/0223193 A1, Jul. 4, 2024
Int. Cl. H03L 7/081 (2006.01); H03L 7/087 (2006.01); H03L 7/089 (2006.01)
CPC H03L 7/081 (2013.01) [H03L 7/087 (2013.01); H03L 7/0895 (2013.01)] 14 Claims
OG exemplary drawing
 
1. A phase-locked loop device, comprising:
a frequency-locked loop circuit, comprising:
a delay generator circuit, receiving a feedback clock signal, generating a first ramp signal according to the feedback clock signal, and comparing the first ramp signal with a plurality of reference voltages to generate a plurality of delayed feedback clock signals; and
a frequency-phase detector, coupled to the delay generator circuit and receiving a reference clock signal, the frequency-phase detector having a dead zone control mechanism, generating a locking signal based on a comparison between phases of the reference clock signal and the plurality of delayed feedback clock signals, and automatically switching on/off the dead zone; and
a phase-locked loop circuit, coupled to the frequency-locked loop circuit and receiving the reference clock signal, and generating a first output current according to a phase difference between the reference clock signal and the feedback clock signal.