US 12,289,110 B2
Phase correction circuit, and clock buffer and semiconductor apparatus including the same
Ji Hyo Kang, Icheon-si (KR)
Assigned to SK hynix Inc., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on Nov. 3, 2023, as Appl. No. 18/501,517.
Application 18/501,517 is a division of application No. 17/585,241, filed on Jan. 26, 2022, granted, now 11,824,544.
Claims priority of application No. 10-2021-0108093 (KR), filed on Aug. 17, 2021.
Prior Publication US 2024/0063781 A1, Feb. 22, 2024
Int. Cl. H03K 5/15 (2006.01); G11C 7/22 (2006.01); G11C 11/4076 (2006.01); H03K 5/135 (2006.01)
CPC H03K 5/15013 (2013.01) [G11C 7/222 (2013.01); G11C 11/4076 (2013.01); H03K 5/135 (2013.01)] 9 Claims
OG exemplary drawing
 
1. A clock buffer comprising:
a phase separator configured to receive an external clock signal and generate multi-phase clock signals; and
a phase correction circuit coupled to a plurality of signal paths for transmitting the multi-phase clock signals, the phase correction circuit configured to correct phase skew among the multi-phase clock signals by averaging the phases of two signals which are obtained by synthesizing a signal of each of the signal paths with another signal of a signal path different from the corresponding signal path,
wherein the phase correction circuit comprises:
a first correction loop configured to synthesize two adjacent signals based on the plurality of signal paths among the multi-phase clock signals; and
a second correction loop configured to synthesize complementary signals among the multi-phase clock signals.