US 12,289,103 B2
Trap circuits for use with differential capacitively-coupled resonant clock networks
Bouchaib Cherif, Yorktown Heights, NY (US); and Max Earl Nielsen, Pocatello, ID (US)
Assigned to Microsoft Technology Licensing, LLC, Redmond, WA (US)
Filed by Microsoft Technology Licensing, LLC, Redmond, WA (US)
Filed on Mar. 8, 2021, as Appl. No. 17/194,547.
Prior Publication US 2022/0286136 A1, Sep. 8, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H03K 19/195 (2006.01); H03K 19/00 (2006.01); H03K 19/0185 (2006.01); H10N 60/80 (2023.01)
CPC H03K 19/195 (2013.01) [H03K 19/0016 (2013.01); H03K 19/018521 (2013.01); H10N 60/805 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A superconducting integrated circuit comprising:
a first superconducting circuit comprising: (1) a first Josephson junction coupled via a first capacitor to a first clock line, wherein the first capacitor is configured to receive a first clock signal having a first phase via the first clock line and couple a first bias current to the first Josephson junction, and (2) a second Josephson junction coupled via a second capacitor to a second clock line, wherein the second capacitor is configured to receive a second clock signal having a second phase, different from the first phase, via the second clock line and couple a second bias current to the second Josephson junction;
a second superconducting circuit comprising: (1) a third Josephson junction coupled via a third capacitor to the first clock line, wherein the third capacitor is configured to receive the first clock signal having the first phase via the first clock line and couple a third bias current to the third Josephson junction, and (2) a fourth Josephson junction coupled via a fourth capacitor to the second clock line, wherein the fourth capacitor is configured to receive the second clock signal having the second phase via the second clock line and couple a fourth bias current to the fourth Josephson junction;
a first trap circuit coupled between the first capacitor and the first Josephson junction, wherein the first trap circuit is configured to attenuate any signals generated by a triggering of the first Josephson junction to reduce crosstalk between the first Josephson junction and the third Josephson junction; and
a second trap circuit coupled between the second capacitor and the second Josephson junction, wherein the second trap circuit is configured to attenuate any signals generated by a triggering of the second Josephson junction to reduce crosstalk between the second Josephson junction and the fourth Josephson junction.