| CPC H03K 19/0005 (2013.01) [H03K 19/018585 (2013.01)] | 10 Claims |
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1. An impedance calibration circuit comprising:
a first leg set in which among first to third duplicate legs, the first duplicate leg is connected to an external resistor through a first node and the second duplicate leg and the third duplicate leg are connected to a second node, an impedance of the first leg set being calibrated to a first target impedance according to a first impedance control code and a second impedance control code during an activation period of a first timing control signal;
a second leg set in which among fourth to sixth duplicate legs, the fourth duplicate leg is connected to the external resistor and the fifth duplicate leg and the sixth duplicate leg are connected to the second node, an impedance of the second leg set being calibrated to a second target impedance according to the first impedance control code and the second impedance control code during an activation period of a second timing control signal;
a first code generation circuit configured to calibrate and output a value of the first impedance control code according to a result of comparing a voltage of the first node with a reference voltage, and to generate a first hold signal by detecting a completion state of the calibration of the first impedance control code;
a second code generation circuit configured to calibrate and output a value of the second impedance control code according to a result of comparing a voltage of the second node with the reference voltage, and to generate a second hold signal by detecting a completion state of the calibration of the second impedance control code; and
a timing control signal generation circuit configured to generate the first timing control signal and the second timing control signal having different activation periods in response to an impedance calibration enable signal and at least one of the first hold signal and the second hold signal.
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