US 12,289,083 B2
Communication device
Hajime Kimura, Kanagawa (JP); and Takayuki Ikeda, Kanagawa (JP)
Assigned to SEMICONDUCTOR ENERGY LABORATORY CO., LTD., Kanagawa-ken (JP)
Appl. No. 17/611,921
Filed by SEMICONDUCTOR ENERGY LABORATORY CO., LTD., Atsugi (JP)
PCT Filed May 19, 2020, PCT No. PCT/IB2020/054711
§ 371(c)(1), (2) Date Nov. 17, 2021,
PCT Pub. No. WO2020/240339, PCT Pub. Date Dec. 3, 2020.
Claims priority of application No. 2019-102029 (JP), filed on May 31, 2019; and application No. 2019-102036 (JP), filed on May 31, 2019.
Prior Publication US 2022/0255511 A1, Aug. 11, 2022
Int. Cl. H03F 3/45 (2006.01); H03F 3/19 (2006.01); H04B 1/40 (2015.01)
CPC H03F 3/19 (2013.01) [H03F 2200/451 (2013.01); H04B 1/40 (2013.01)] 12 Claims
OG exemplary drawing
 
1. A communication device comprising an amplifier circuit,
wherein the amplifier circuit comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a first load, a second load, a third load, a fourth load, a first terminal, a second terminal, a third terminal, and a fourth terminal,
wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor,
wherein one of a source and a drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor,
wherein one of a source and a drain of the fifth transistor is electrically connected to one of a source and a drain of the sixth transistor,
wherein one of a source and a drain of the seventh transistor is electrically connected to one of a source and a drain of the eighth transistor,
wherein the other of the source and the drain of the first transistor and the other of the source and the drain of the third transistor are electrically connected to a first power supply line,
wherein the other of the source and the drain of the fifth transistor and the other of the source and the drain of the seventh transistor are electrically connected to a second power supply line,
wherein a gate of the second transistor and a gate of the fourth transistor are electrically connected to a first wiring,
wherein a gate of the sixth transistor and a gate of the eighth transistor are electrically connected to a second wiring,
wherein the first terminal is electrically connected to the gate of the first transistor, the other of the source and the drain of the sixth transistor, and the first load,
wherein the second terminal is electrically connected to the gate of the third transistor, the other of the source and the drain of the eighth transistor, and the second load,
wherein the third terminal is electrically connected to the gate of the fifth transistor, the other of the source and the drain of the second transistor, and the third load, and
wherein the fourth terminal is electrically connected to the gate of the seventh transistor, the other of the source and the drain of the fourth transistor, and the fourth load.