US 12,289,050 B1
Method and apparatus for delivering power to semiconductors
Patrizio Vinciarelli, Boston, MA (US); and Andrew T. D'Amico, Beverly Hills, CA (US)
Assigned to Vicor Corporation, Andover, MA (US)
Filed by Vicor Corporation, Andover, MA (US)
Filed on Mar. 28, 2024, as Appl. No. 18/619,864.
Application 16/299,243 is a division of application No. 15/616,288, filed on Jun. 7, 2017, granted, now 10,277,105, issued on Apr. 30, 2019.
Application 18/619,864 is a continuation of application No. 17/876,715, filed on Jul. 29, 2022, granted, now 11,984,806.
Application 17/876,715 is a continuation of application No. 17/578,065, filed on Jan. 18, 2022, granted, now 11,728,729, issued on Aug. 15, 2023.
Application 17/578,065 is a continuation of application No. 16/991,608, filed on Aug. 12, 2020, granted, now 11,233,447, issued on Jan. 25, 2022.
Application 16/991,608 is a continuation of application No. 16/299,243, filed on Mar. 12, 2019, granted, now 10,784,765, issued on Sep. 22, 2020.
Application 15/616,288 is a continuation in part of application No. 15/091,346, filed on Apr. 5, 2016, granted, now 10,158,357, issued on Dec. 18, 2018.
Int. Cl. H02M 3/155 (2006.01); H01L 23/538 (2006.01); H01L 23/64 (2006.01); H01L 25/18 (2023.01); H02J 3/00 (2006.01); H02M 1/08 (2006.01); H02M 3/335 (2006.01); H02M 1/00 (2006.01)
CPC H02M 3/155 (2013.01) [H01L 23/5383 (2013.01); H01L 23/5384 (2013.01); H01L 23/5385 (2013.01); H01L 23/5386 (2013.01); H01L 23/645 (2013.01); H01L 25/18 (2013.01); H02J 3/00 (2013.01); H02M 1/08 (2013.01); H02M 3/33576 (2013.01); H02M 1/008 (2021.05)] 41 Claims
OG exemplary drawing
 
1. A method of supplying power received from an input source at a source voltage to circuitry on a semiconductor chip mounted in a semiconductor package at a DC load voltage, comprising:
at the semiconductor package, receiving power at a package voltage having an average voltage of essentially zero volts;
performing a second power conversion at a point-of-load (POL) circuit located within the semiconductor package, the second power conversion including receiving the power at the package voltage, making a second voltage adjustment, and delivering power to the semiconductor chip at a chip voltage; and
performing a third power conversion in circuitry located on the semiconductor chip, the third conversion including receiving power from the POL circuit, making a third voltage adjustment, and delivering power at the load voltage to the circuitry on the semiconductor chip;
wherein the package voltage is at least, 5, times greater than the load voltage.