US 12,289,048 B2
Semiconductor module
Ryota Kojima, Nisshin (JP); and Akihiro Yamaguchi, Nisshin (JP)
Assigned to DENSO CORPORATION, Kariya (JP); TOYOTA JIDOSHA KABUSHIKI KAISHA, Toyota (JP); and MIRISE Technologies Corporation, Nisshin (JP)
Filed by DENSO CORPORATION, Kariya (JP); TOYOTA JIDOSHA KABUSHIKI KAISHA, Toyota (JP); and MIRISE Technologies Corporation, Nisshin (JP)
Filed on Apr. 11, 2022, as Appl. No. 17/717,426.
Claims priority of application No. 2021-073508 (JP), filed on Apr. 23, 2021.
Prior Publication US 2022/0344286 A1, Oct. 27, 2022
Int. Cl. H01L 23/00 (2006.01); H01L 23/498 (2006.01); H01L 23/64 (2006.01); H02M 1/44 (2007.01); H02M 3/00 (2006.01)
CPC H02M 1/44 (2013.01) [H02M 3/003 (2021.05); H01L 2224/32225 (2013.01); H01L 2924/13055 (2013.01); H01L 2924/19041 (2013.01)] 12 Claims
OG exemplary drawing
 
1. A semiconductor module comprising:
a substrate having a front surface, a rear surface opposite to the front surface, a front-surface wiring disposed on the front surface, and a rear-surface wiring disposed on the rear surface;
at least one semiconductor package including a semiconductor chip and a pad electrically connected to the semiconductor chip, the semiconductor chip including a switching element, the at least one semiconductor package disposed to the substrate in a state where the pad is electrically connected to the rear-surface wiring;
a housing to which the substrate is fixed in a state where the at least one semiconductor package is thermally connected to the housing; and
at least one Y capacitor, wherein
the front-surface wiring includes a front-surface ground wiring electrically connected to the housing, and a front-surface main wiring electrically connected to the rear-surface wiring that is electrically connected to the at least one semiconductor package,
the at least one Y capacitor is disposed on the front surface of the substrate at a position facing the at least one semiconductor package and between the front-surface ground wiring and the front-surface main wiring, and
the at least one semiconductor package and the at least one Y capacitor are disposed in such a manner that a direction of electric current flowing in the at least one semiconductor package and a direction of electric current flowing in the at least one Y capacitor are opposite to each other.