US 12,289,047 B2
Power stealing using a current transformer
Navaneeth Kumar Narayanasamy, Coimbatore (IN); and Manu Balakrishnan, Kollam (IN)
Assigned to TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed by Texas Instruments Incorporated, Dallas, TX (US)
Filed on Feb. 26, 2024, as Appl. No. 18/587,119.
Application 18/587,119 is a continuation of application No. 17/406,762, filed on Aug. 19, 2021, granted, now 11,962,234.
Prior Publication US 2024/0195285 A1, Jun. 13, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H02M 1/08 (2006.01); H02M 1/088 (2006.01); H02M 1/32 (2007.01); H02M 7/217 (2006.01)
CPC H02M 1/088 (2013.01) [H02M 1/32 (2013.01); H02M 7/217 (2013.01)] 12 Claims
OG exemplary drawing
 
1. A circuit, comprising:
a first gate driver having a first gate driver input and a first gate driver output, wherein the first gate driver output is adaptable to be coupled to a first transistor;
a second gate driver having a second gate driver input and a second gate driver output, wherein the second gate driver output is adaptable to be coupled to a second transistor;
a third gate driver having a third gate driver input and a third gate driver output, wherein the third gate driver output is adaptable to be coupled to a third transistor;
a fourth gate driver having a fourth gate driver input and a fourth gate driver output, wherein the fourth gate driver adaptable to be coupled to a fourth transistor; and
a pulse width modulation (PWM) controller having first, second, third, and fourth PWM outputs coupled to respective first, second, third, and fourth gate driver inputs, wherein the PWM controller provides respective first, second, third, and fourth gate signals at the first, second, third, and fourth PWM outputs, respectively, in a repeating pattern that includes:
a first pattern portion wherein the second and third PWM outputs are asserted and the first and fourth PWM outputs are deasserted;
a second pattern portion in which the first and second PWM outputs are asserted and the third and fourth PWM outputs are deasserted;
a third pattern portion in which the first and fourth PWM outputs are asserted and the second and third PWM outputs are deasserted; and
a fourth pattern portion in which the third and fourth PWM outputs are asserted and the first and second gate signals are deasserted.