US 12,288,964 B2
Method for manufacturing optical semiconductor waveguide window structure
Naoki Fujiwara, Musashino (JP); Takahiko Shindo, Musashino (JP); Shigeru Kanazawa, Musashino (JP); and Meishin Chin, Musashino (JP)
Assigned to Nippon Telegraph and Telephone Corporation, Tokyo (JP)
Appl. No. 17/618,789
Filed by Nippon Telegraph and Telephone Corporation, Tokyo (JP)
PCT Filed Jun. 17, 2019, PCT No. PCT/JP2019/023812
§ 371(c)(1), (2) Date Dec. 13, 2021,
PCT Pub. No. WO2020/255183, PCT Pub. Date Dec. 24, 2020.
Prior Publication US 2022/0239066 A1, Jul. 28, 2022
Int. Cl. H01S 5/16 (2006.01); G02B 6/42 (2006.01); H01S 5/026 (2006.01); H01S 5/12 (2021.01); H01S 5/227 (2006.01)
CPC H01S 5/1231 (2013.01) [G02B 6/4207 (2013.01); H01S 5/0265 (2013.01); H01S 5/16 (2013.01); H01S 5/2275 (2013.01); H01S 5/164 (2013.01)] 4 Claims
OG exemplary drawing
 
1. A method for manufacturing a semiconductor light source element, the method comprising:
forming an active layer on an InP substrate, wherein the active layer is a crystal grown layer and wherein a crystal orientation of a surface thereof was a (1 0 0) plane and an orientation flat thereof was a (0 −1 −1) plane;
forming a first etching mask on the active layer, and removing a part of the active layer, wherein a remaining part of the active layer is perpendicular to the orientation flat;
forming an EA (Electro-Absorption) layer, wherein the EA layer is a crystal grown layer and wherein the EA layer forms a core layer of an EA modulator, without removing the first etching mask;
removing the first etching mask and forming a second etching mask on the active layer;
partially removing the EA layer, such that a region serving as a window structure remains, wherein the region remaining is wider than a mesa stripe;
removing the second etching mask and then forming the window structure by forming an overclad layer on an entire surface; and
forming a third etching mask on the overclad layer, and then forming the mesa stripe by removing each of the overclad layer, the active layer, the EA layer, and a part of the InP substrate, wherein the mesa strip has a height of at least 3 μm.