US 12,288,807 B2
Amorphization and regrowth of source-drain regions from the bottom-side of a semiconductor assembly
Aaron Lilak, Beaverton, OR (US); Rishabh Mehandru, Portland, OR (US); Willy Rachmady, Beaverton, OR (US); Harold Kennel, Portland, OR (US); and Tahir Ghani, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Sep. 13, 2023, as Appl. No. 18/367,843.
Application 18/367,843 is a division of application No. 16/457,690, filed on Jun. 28, 2019, granted, now 11,798,991.
Prior Publication US 2024/0006489 A1, Jan. 4, 2024
Int. Cl. H01L 29/08 (2006.01); H01L 21/02 (2006.01); H01L 21/8238 (2006.01)
CPC H01L 29/0847 (2013.01) [H01L 21/02356 (2013.01); H01L 21/02592 (2013.01); H01L 21/823807 (2013.01); H01L 21/823814 (2013.01); H01L 21/823828 (2013.01); H01L 21/823871 (2013.01)] 9 Claims
OG exemplary drawing
 
1. A method, comprising:
forming a carrier wafer;
forming a semiconductor structure on the carrier wafer that includes a channel, a first source-drain region adjacent a first portion of the channel, a second source-drain region adjacent a second portion of the channel, and a gate conductor on the channel;
forming sacrificial material to cover the first source-drain region and the second source-drain region;
inverting the carrier wafer;
removing the carrier wafer;
removing the sacrificial material;
forming a first implant in the first source-drain region and forming a second implant in the second source-drain region while blocking implantation into the channel region, wherein forming the first implant and the second implant is performing by implanting the first source-drain region and the second source-drain region from a side of the channel opposite the gate conductor;
performing a thermal anneal; and
forming a first source-drain contact on the bottom-side of the first source-drain region and a second source-drain contact on the bottom-side of the second source-drain region.