| CPC H01L 29/0665 (2013.01) [H01L 29/0653 (2013.01); H01L 29/6656 (2013.01); H01L 29/78618 (2013.01); H01L 29/78696 (2013.01)] | 20 Claims |
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1. A method of manufacturing an integrated circuit device, the method comprising:
forming a structure including a fin-type active region, extending in a first horizontal direction on a substrate, and a channel region on the fin-type active region;
forming a dummy gate layer extending in a second horizontal direction crossing the first horizontal direction on the channel region;
forming an insulating spacer layer covering a sidewall of the dummy gate layer;
forming a sacrificial insulating layer conformally covering the insulating spacer layer;
forming a recess exposing the channel region on the fin-type active region by removing a portion of each of the sacrificial insulating layer and the insulating spacer layer, and forming an insulating spacer including a portion covering the sidewall of the dummy gate layer;
forming a source/drain region connected to the channel region in the recess and including a first portion facing the sidewall of the dummy gate layer with the sacrificial insulating layer and the insulating spacer therebetween;
forming a first space between the insulating spacer and the first portion of the source/drain region by removing the sacrificial insulating layer;
forming an insulating liner covering the insulating spacer and the source/drain region and defining an air gap including at least a portion of the first space;
forming a gate space on the channel region by removing the dummy gate layer; and
forming a gate line in the gate space.
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