US 12,288,802 B2
Structure and method for forming integrated high density MIM capacitor
Hsien-Wei Chen, Hsinchu (TW); Ying-Ju Chen, Tuku Township (TW); Jie Chen, New Taipei (TW); and Ming-Fa Chen, Taichung (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on May 3, 2024, as Appl. No. 18/654,658.
Application 17/872,701 is a division of application No. 16/901,912, filed on Jun. 15, 2020, granted, now 11,715,755, issued on Aug. 1, 2023.
Application 18/654,658 is a continuation of application No. 17/872,701, filed on Jul. 25, 2022, granted, now 12,009,386.
Prior Publication US 2024/0290823 A1, Aug. 29, 2024
Int. Cl. H01L 23/522 (2006.01); H01G 4/30 (2006.01); H01L 21/768 (2006.01); H01L 49/02 (2006.01)
CPC H01L 28/60 (2013.01) [H01G 4/30 (2013.01); H01L 21/76802 (2013.01); H01L 21/76877 (2013.01); H01L 23/5223 (2013.01); H01L 23/5226 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A package device comprising:
a device layer, one or more metallization layers over the device layer;
an interconnect structure overlying the device layer, the interconnect structure including one or more metallization layers embedded within one or more dielectric layer, respectively, a topmost metallization layer of the one or more metallization layers including a first contact pad;
a Metal-Insulator-Metal (MIM) capacitor structure overlying the interconnect structure, the MIM capacitor structure including:
a first metallization layer having therein a first capacitor plate and a first dummy plate, electrically isolated from the first capacitor plate, the first capacitor plate and the first dummy plate having co-planar respective top surfaces;
a capacitor dielectric layer overlying the first metallization layer;
a second metallization layer having therein a second capacitor plate and a second dummy plate, electrically isolated from the second capacitor plate, the second capacitor plate and the second dummy plate having co-planar respective top surfaces;
a passivation layer overlying the MIM capacitor structure and having a planar top surface;
a second contact pad on the passivation layer; and
a conductive via extending through the passivation layer.