US 12,288,791 B2
Semiconductor device and method
Yu-Rung Hsu, Tainan (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Aug. 4, 2023, as Appl. No. 18/365,415.
Application 18/365,415 is a division of application No. 17/351,444, filed on Jun. 18, 2021, granted, now 11,887,985.
Claims priority of provisional application 63/156,440, filed on Mar. 4, 2021.
Prior Publication US 2024/0021620 A1, Jan. 18, 2024
Int. Cl. H01L 27/092 (2006.01); H01L 21/8234 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01)
CPC H01L 27/0924 (2013.01) [H01L 21/823418 (2013.01); H01L 21/823431 (2013.01); H01L 29/66795 (2013.01); H01L 29/7851 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A device comprising:
a channel region over a first semiconductor strip;
a gate stack over sidewalls and a top surface of the channel region, wherein the channel region comprises:
a first portion having a first width; and
a second portion under the first portion and having a second width, wherein the second width is smaller than the first width; and
a source/drain region on a side of the channel region, wherein at an interface between the source/drain region and the second portion of the channel region, surfaces of the second portion of the channel region are in the (110) family of crystallographic planes.