US 12,288,747 B2
Multi-dimensional metal first device layout and circuit design
H. Jim Fulford, Marianna, FL (US); Mark I. Gardner, Cedar Creek, TX (US); and Partha Mukhopadhyay, Oviedo, FL (US)
Assigned to Tokyo Electron Limited, Tokyo (JP)
Filed by Tokyo Electron Limited, Tokyo (JP)
Filed on May 10, 2022, as Appl. No. 17/740,691.
Claims priority of provisional application 63/235,277, filed on Aug. 20, 2021.
Prior Publication US 2023/0057139 A1, Feb. 23, 2023
Int. Cl. H01L 23/522 (2006.01); H01L 21/3105 (2006.01); H01L 21/762 (2006.01)
CPC H01L 23/5226 (2013.01) [H01L 21/31053 (2013.01); H01L 21/762 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method for fabricating a semiconductor structure, comprising:
forming a stack of metal structures on a substrate, the stack of metal structures including multiple metal structures that are vertically stacked over and electrically separated from one another, each of the metal structures including a ring and one or more pad contacts extending from the ring, the rings of the metal structures being vertically aligned with one another;
forming one or more channel structures within the rings of the metal structures, the channel structures being electrically separated from one another and electrically separated from the substrate; and
forming one or more interconnections that extend from a position above the stack of metal structures to corresponding one or more of the pad contacts of the metal structures.