US 12,288,746 B2
Skip level vias in metallization layers for integrated circuit devices
Adel Elsherbini, Tempe, AZ (US); Mauro Kobrinsky, Portland, OR (US); Shawna Liff, Scottsdale, AZ (US); Johanna Swan, Scottsdale, AZ (US); Gerald Pasdast, San Jose, CA (US); and Sathya Narasimman Tiagaraj, Chandler, AZ (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Dec. 26, 2019, as Appl. No. 16/727,747.
Prior Publication US 2021/0202377 A1, Jul. 1, 2021
Int. Cl. H01L 23/52 (2006.01); H01L 21/768 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01)
CPC H01L 23/5226 (2013.01) [H01L 21/76816 (2013.01); H01L 21/76877 (2013.01); H01L 23/5283 (2013.01); H01L 23/5286 (2013.01)] 8 Claims
OG exemplary drawing
 
1. An integrated circuit (IC) die, comprising:
a transistor;
a first interconnect level over the transistor, the first interconnect level comprising a signal pad or trace embedded within a first dielectric material and coupled to the transistor;
a second interconnect level over the first interconnect level, the second interconnect level comprising a power pad or trace embedded within a second dielectric material and coplanar with a ground pad or trace; and
a third interconnect level over the second interconnect level and comprising a plurality of adjacent vias embedded within a third dielectric material, wherein a first of the vias is in contact with the power pad or trace, a second of the vias is in contact with the ground pad or trace, and a third of the vias extends between the coplanar power and ground pads or traces, and is in contact with the signal pad or trace, and
wherein the third of the vias is continuous from above an uppermost surface of the coplanar power and ground pads or traces to below a bottommost surface of the coplanar power and ground pads or traces.