| CPC H01L 23/49833 (2013.01) [H01L 23/3128 (2013.01); H01L 24/16 (2013.01); H01L 24/32 (2013.01); H01L 24/73 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/16235 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/73204 (2013.01)] | 19 Claims |
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1. A semiconductor package, comprising:
a lower substrate that includes a lower wiring layer;
a semiconductor chip disposed on the lower substrate, wherein the semiconductor chip is electrically connected to the lower wiring layer;
an upper substrate disposed on the semiconductor chip, wherein the upper substrate includes a lower surface that faces the semiconductor chip, an upper wiring layer, and a plurality of protruding structures disposed below the lower surface;
a connection structure disposed between the lower substrate and the upper substrate, wherein the connection structure electrically connects the lower wiring layer and the upper wiring layer;
an encapsulant that fills a space between the lower substrate and the upper substrate, and seals at least a portion of each of the semiconductor chip and the connection structure; and
a connection bump disposed below the lower substrate, wherein the connection bump is electrically connected to the lower wiring layer,
wherein the lower surface of the upper substrate includes a cavity region that overlaps the semiconductor chip in a first direction that is perpendicular to the lower surface, and a plurality of channel regions that extend from the cavity region to an edge of the upper substrate,
wherein the cavity region and the plurality of channel regions are defined by the plurality of protruding structures.
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