| CPC H01L 21/823878 (2013.01) [H01L 21/76232 (2013.01); H01L 21/823814 (2013.01); H01L 21/823821 (2013.01); H01L 21/823871 (2013.01); H01L 27/0924 (2013.01)] | 20 Claims |
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1. A method, comprising:
forming first and second gate stacks extending across a semiconductor fin on a substrate;
forming source/drain regions in the semiconductor fin, wherein one of the source/drain region is between the first and second gate stacks;
forming a dielectric layer laterally surrounding the first and second gate stacks;
forming a mask layer covering the first gate stack, while at least leaving the a first portion of the dielectric layer between the first and second gate stacks exposed;
with the mask layer in place, doping the first portion of the dielectric layer between the first and second gate stacks with a dopant;
removing the second gate stack to form a gate trench next to the doped first portion of the dielectric layer;
performing an annealing process to expand the doped first portion of the dielectric layer toward the gate trench;
forming an isolation structure in the gate trench and next to the expanded first portion of the dielectric layer; and
forming a source/drain contact extending through the dielectric layer to the one of the source/drain regions.
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