US 12,288,722 B2
Spacer structure for semiconductor device and method for forming the same
Han-Yu Lin, Nantou County (TW); Jhih-Rong Huang, Hsinchu (TW); Yen-Tien Tung, Hsinchu (TW); Tzer-Min Shen, Hsinchu (TW); Fu-Ting Yen, Hsinchu (TW); Gary Chan, Hsinchu (TW); Keng-Chu Lin, Ping-Tung (TW); Li-Te Lin, Hsinchu (TW); and Pinyen Lin, Rochester, NY (US)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Jan. 2, 2023, as Appl. No. 18/149,130.
Application 18/149,130 is a continuation of application No. 17/143,698, filed on Jan. 7, 2021, granted, now 11,545,397.
Claims priority of provisional application 63/052,243, filed on Jul. 15, 2020.
Prior Publication US 2023/0141093 A1, May 11, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 21/8234 (2006.01); H01L 21/3065 (2006.01); H01L 29/66 (2006.01); H01L 29/786 (2006.01)
CPC H01L 21/823431 (2013.01) [H01L 21/3065 (2013.01); H01L 21/823418 (2013.01); H01L 29/66553 (2013.01); H01L 29/78696 (2013.01)] 20 Claims
OG exemplary drawing
 
16. A method, comprising:
growing, on a substrate, a plurality of channel layers and a plurality of sacrificial layers alternately stacking with each other;
removing, from side surfaces of the plurality of sacrificial layers, a portion of each of the plurality of sacrificial layers to form a plurality of recess structures;
forming a dielectric layer in the plurality of recess structures and on side surfaces of the plurality of channel layers; and
selectively etching the dielectric layer to form a plurality of inner spacer structures, comprising:
performing a first oxygen-free etching process, wherein the dielectric layer is etched at a first etching rate; and
performing a second oxygen-free etching process, wherein the dielectric layer is etched at a second etching rate less than the first etching rate.