US 12,288,715 B2
Semiconductor device and manufacturing method thereof
Yi-Hua Cheng, Chiayi County (TW); Ya-Wen Chiu, Tainan (TW); Yi Che Chan, Hsinchu (TW); and Lun-Kuang Tan, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed on Apr. 17, 2023, as Appl. No. 18/135,622.
Application 18/135,622 is a division of application No. 17/197,995, filed on Mar. 10, 2021, granted, now 11,631,612.
Claims priority of provisional application 63/030,153, filed on May 26, 2020.
Prior Publication US 2023/0253246 A1, Aug. 10, 2023
Int. Cl. H01L 21/768 (2006.01); H01L 21/02 (2006.01); H01L 29/417 (2006.01); H01L 29/45 (2006.01)
CPC H01L 21/7682 (2013.01) [H01L 21/76831 (2013.01); H01L 21/76832 (2013.01); H01L 21/0206 (2013.01); H01L 21/76804 (2013.01); H01L 29/41791 (2013.01); H01L 29/456 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a gate structure including a gate electrode disposed over a channel region;
a plurality of dielectric layers disposed over the channel region;
a gate contact passing through the plurality of dielectric layers and contacting the gate electrode;
a liner insulating layer disposed on a side wall of the gate contact; and
an air gap disposed between the liner insulating layer and the plurality of dielectric layers,
wherein a piece of polycrystalline or amorphous Si is disposed at a bottom of the air gap.