US 12,288,692 B2
Method of forming a FET structure by selective deposition of film on source/drain contact
Yun Han, Albany, NY (US); Alok Ranjan, Austin, TX (US); Peter Ventzek, Austin, TX (US); Andrew Metz, Albany, NY (US); and Hiroaki Niimi, Cohoes, NY (US)
Assigned to TOKYO ELECTRON LIMITED, Tokyo (JP)
Filed by TOKYO ELECTRON LIMITED, Tokyo (JP)
Filed on Apr. 14, 2022, as Appl. No. 17/721,014.
Claims priority of provisional application 63/179,092, filed on Apr. 23, 2021.
Prior Publication US 2022/0344162 A1, Oct. 27, 2022
Int. Cl. H01L 21/285 (2006.01); H01L 21/02 (2006.01); H10D 30/01 (2025.01); H10D 30/62 (2025.01); H10D 64/01 (2025.01); H10D 64/62 (2025.01)
CPC H01L 21/28518 (2013.01) [H01L 21/02057 (2013.01); H10D 30/024 (2025.01); H10D 30/62 (2025.01); H10D 64/017 (2025.01); H10D 64/62 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A method for manufacturing a FET semiconductor structure, the method comprising:
providing a substrate comprising at least one source/drain contact of at least one FET, the at least one source/drain contact formed adjacent to a dummy gate of the at least one FET;
selectively depositing a TiSi2 film with C54 structure directly on and fully covering the at least one source/drain contact relative to a vertical sidewall of a gate spacer between the at least one source/drain contact and the dummy gate; and
replacing the dummy gate with a replacement metal gate, wherein the selectively depositing the TiSi2 film comprises exposing the substrate to a process gas containing a titanium-containing precursor gas and a silicon-containing precursor gas.