US 12,288,596 B2
Semiconductor memory device, processing system including the same and power control circuit for the same
Chang Hyun Kim, Icheon-si (KR)
Assigned to SK hynix Inc., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on Jan. 27, 2023, as Appl. No. 18/102,597.
Application 18/102,597 is a division of application No. 17/191,499, filed on Mar. 3, 2021, granted, now 11,600,308.
Claims priority of application No. 10-2020-0124672 (KR), filed on Sep. 25, 2020.
Prior Publication US 2023/0197118 A1, Jun. 22, 2023
Int. Cl. G11C 7/00 (2006.01); G11C 5/04 (2006.01); G11C 5/14 (2006.01); H01L 25/065 (2023.01)
CPC G11C 5/147 (2013.01) [G11C 5/04 (2013.01); H01L 25/0657 (2013.01); H01L 2225/06541 (2013.01)] 5 Claims
OG exemplary drawing
 
4. A power control circuit for a plurality of memory dies, the memory dies configured to form a stacked chip package, wherein identifiers are assigned to the memory dies, and each of the memory dies includes a first circuit and a second circuit, the first circuit having a first power terminal and a second power terminal, the power control circuit comprising:
a die determination circuit configured to determine stack positions of the memory dies based on the identifiers of the memory dies to output a die attribute signal; and
a current regulation circuit comprising a switch configured to connect the first power terminal with the second power terminal or disconnect the first power terminal from the second power terminal in response to the die attribute signal, wherein a ground voltage may be applied to the first power terminal and the second power terminal to cut off current consumption of the first circuit in response to the die attribute signal.