US 12,288,580 B2
Memory device and operating method for target refresh operation based on number of accesses
Woongrae Kim, Gyeonggi-do (KR)
Assigned to SK hynix Inc., Gyeonggi-do (KR)
Filed by SK hynix Inc., Gyeonggi-do (KR)
Filed on Mar. 25, 2024, as Appl. No. 18/614,763.
Application 18/614,763 is a division of application No. 17/685,054, filed on Mar. 2, 2022, granted, now 11,967,354.
Claims priority of application No. 10-2021-0155701 (KR), filed on Nov. 12, 2021.
Prior Publication US 2024/0274182 A1, Aug. 15, 2024
Int. Cl. G11C 11/406 (2006.01); G11C 7/10 (2006.01); G11C 11/4072 (2006.01); G11C 11/4096 (2006.01)
CPC G11C 11/40618 (2013.01) [G11C 7/1039 (2013.01); G11C 11/40615 (2013.01); G11C 11/4072 (2013.01); G11C 11/4096 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A semiconductor memory device, comprising:
a memory cell region including a plurality of normal cells and a plurality of row-hammer cells coupled to each of a plurality of rows, wherein the row-hammer cells coupled to an n-th row include a plurality of counting cells suitable for storing a number of accesses to the n-th row, a first flag cell suitable for storing data denoting whether to refresh (n±2)-th adjacent rows of the n-th row, and a second flag cell suitable for storing data denoting whether to refresh (n±3)-th adjacent rows of the n-th row;
a refresh control circuit suitable for:
selecting a sampling address based on the number stored in the counting cells corresponding to an input address when an active command is inputted,
calculating first to third adjacent addresses based on the sampling address, and
outputting a row-hammer address by scheduling the first to third adjacent addresses based on the data stored in the first flag cell and the second flag cell when a target refresh command is issued; and
a row control circuit suitable for refreshing one or more rows corresponding to the row-hammer address according to the target refresh command.