US 12,288,527 B2
Display panel and display apparatus
Ying Han, Beijing (CN); Xuehuan Feng, Beijing (CN); Yicheng Lin, Beijing (CN); Pan Xu, Beijing (CN); Guoying Wang, Beijing (CN); Xing Zhang, Beijing (CN); Zhan Gao, Beijing (CN); and Mingi Chu, Beijing (CN)
Assigned to BOE TECHNOLOGY GROUP CO., LTD, Beijing (CN)
Filed by BOE TECHNOLOGY GROUP CO., LTD., Beijing (CN)
Filed on Jan. 24, 2024, as Appl. No. 18/421,549.
Application 18/421,549 is a continuation of application No. 17/908,021, granted, now 11,900,885, previously published as PCT/CN2021/119181, filed on Sep. 17, 2021.
Prior Publication US 2024/0169928 A1, May 23, 2024
Int. Cl. G09G 3/32 (2016.01); G09G 3/3266 (2016.01); G09G 3/3275 (2016.01); G11C 19/28 (2006.01); H10D 86/40 (2025.01); H10D 86/60 (2025.01); H10K 59/121 (2023.01); H10K 59/131 (2023.01)
CPC G09G 3/3266 (2013.01) [G09G 3/3275 (2013.01); G11C 19/28 (2013.01); H10D 86/441 (2025.01); H10D 86/60 (2025.01); H10K 59/1213 (2023.02); H10K 59/1216 (2023.02); H10K 59/1315 (2023.02); G09G 2300/0842 (2013.01); G09G 2310/0278 (2013.01); G09G 2310/0286 (2013.01); G09G 2310/061 (2013.01); G09G 2320/0233 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A display panel, comprising:
a substrate;
a plurality of sub-pixels disposed on a side of the substrate; the plurality of sub-pixels being arranged in a plurality of rows and a plurality of columns, sub-pixels in a row being arranged in a first direction and sub-pixels in a column being arranged in a second direction; and a sub-pixel including a pixel drive circuit and a light-emitting device electrically connected to the pixel drive circuit; and
a gate drive circuit located on a same side of the substrate as the plurality of sub-pixels, wherein the gate drive circuit includes a plurality of cascaded shift registers, and a shift register is electrically connected to a plurality of pixel drive circuits in a row of sub-pixels; the shift register includes a plurality of device groups, and a device group is located in a region between two adjacent sub-pixels in the corresponding row of sub-pixels; and the device group includes at least one transistor and/or at least one capacitor; wherein
the gate drive circuit further includes a plurality of cascade input signal lines and a plurality of cascade display reset signal lines; a cascade input signal line is configured to connect a shift signal terminal of one shift register and an input signal terminal of another shift register; and a cascade display reset signal line is configured to connect a shift signal terminal of one shift register and a display reset signal terminal of another shift register; and
the display panel has a plurality of sub-pixel regions for arranging the plurality of sub-pixels and first gap regions each located between two adjacent columns of sub-pixel regions; and the cascade display reset signal lines and the cascade input signal lines are disposed in the first gap regions, and both are disposed in different first gap regions; wherein
among device groups included in different shift registers, device groups with a same structure are located in a same region between two adjacent columns of sub-pixels; and/or
no device group is arranged in first gap regions where the cascade display reset signal lines or the cascade input signal lines are disposed; and/or
in the second direction, any three adjacent rows of sub-pixel regions are a first row of sub-pixel regions, a second row of sub-pixel regions, and a third row of sub-pixel regions, the pixel drive circuit includes a first sensing signal line located in a third gap region and extending along the first direction; and the plurality of sub-pixels are divided into a plurality of pixel units, and a pixel unit includes at least three sub-pixels arranged in sequence in the first direction; and in sub-pixels located in the second row of sub-pixel regions and the third row of sub-pixel regions, two pixel units opposite to each other in the second direction share the first sensing signal line.