US 12,288,520 B2
Method and system for CMOS-like logic gates using TFTs and applications therefor
Sheida Gohardehi, Waterloo (CA); Manoj Sachdev, Waterloo (CA); Qing Li, Cupertino, CA (US); and William Wong, Waterloo (CA)
Appl. No. 18/281,516
Filed by Sheida Gohardehi, Waterloo (CA); Manoj Sachdev, Waterloo (CA); Qing Li, Cupertino, CA (US); and William Wong, Waterloo (CA)
PCT Filed Mar. 11, 2022, PCT No. PCT/CA2022/050364
§ 371(c)(1), (2) Date Sep. 11, 2023,
PCT Pub. No. WO2022/187969, PCT Pub. Date Sep. 15, 2022.
Claims priority of provisional application 63/207,641, filed on Mar. 12, 2021.
Claims priority of provisional application 63/211,751, filed on Jun. 17, 2021.
Prior Publication US 2024/0169913 A1, May 23, 2024
Int. Cl. G09G 3/3233 (2016.01); H01L 29/786 (2006.01)
CPC G09G 3/3233 (2013.01) [G09G 2300/0465 (2013.01); G09G 2300/0852 (2013.01); G09G 2310/0286 (2013.01); G09G 2310/08 (2013.01); G09G 2330/021 (2013.01); H01L 29/78669 (2013.01)] 13 Claims
OG exemplary drawing
 
1. A CMOS-like logic gate comprising:
a set of thin-film-transistors (TFTs), the set of TFTs including a subset of pull down TFTs, a subset of diode-connected TFTs and an output pull-up transistor; and
a capacitor;
wherein the subset of diode-connected TFTs, the output pull-up transistor and the capacitor are positioned to provide a bootstrapped feedback network to provide full-output swing; and
wherein the subset of diode-connected TFTs and one of the subset of pull-down TFTs form a leakage current path; and
wherein at least one of the subset of pull-down TFTs is connected to a first input.