US 12,288,519 B2
Display substrate, driving method thereof, and display apparatus
Tiaomei Zhang, Beijing (CN); Ziyang Yu, Beijing (CN); Wenbo Chen, Beijing (CN); and Haigang Qing, Beijing (CN)
Assigned to Chengdu BOE Optoelectronics Technology Co., Ltd., Sichuan (CN); and BOE Technology Group Co., Ltd., Beijing (CN)
Appl. No. 18/269,766
Filed by Chengdu BOE Optoelectronics Technology Co., Ltd., Sichuan (CN); and BOE Technology Group Co., Ltd., Beijing (CN)
PCT Filed Dec. 23, 2021, PCT No. PCT/CN2021/140857
§ 371(c)(1), (2) Date Jun. 27, 2023,
PCT Pub. No. WO2023/115457, PCT Pub. Date Jun. 29, 2023.
Prior Publication US 2025/0006122 A1, Jan. 2, 2025
Int. Cl. G09G 3/3233 (2016.01)
CPC G09G 3/3233 (2013.01) [G09G 2300/0426 (2013.01); G09G 2300/0842 (2013.01); G09G 2310/061 (2013.01); G09G 2310/08 (2013.01); G09G 2320/0233 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A display substrate, comprising a plurality of sub-pixels, wherein at least one of the plurality of sub-pixels comprises a pixel drive circuit and a light emitting device, the pixel drive circuit comprises an initial signal line, a reset signal line and a plurality of transistors, and the initial signal line comprises a first branch;
the plurality of transistors comprise a drive transistor configured to provide a drive current to the light emitting device, a first reset transistor configured to reset a gate of the drive transistor through the first branch of the initial signal line under control of the reset signal line, and a second reset transistor configured to reset a first terminal of the light emitting device through the first branch of the initial signal line under the control of the reset signal line; and
the first reset transistor and the second reset transistor in a same sub-pixel are controlled by a same reset signal line;
wherein in a plane perpendicular to the display substrate, the display substrate comprises a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer, that are arranged in sequence on a substrate, and an insulating layer arranged between the semiconductor layer and the first conductive layer or insulating layers between respective conductive layers;
the semiconductor layer comprises active layers of a plurality of transistors and the first branch of the initial signal line, the first conductive layer comprises gate electrodes of the plurality of transistors, the reset signal line and a first electrode plate of a storage capacitor, the second conductive layer comprises a second electrode plate of the storage capacitor, the third conductive layer comprises a second connection electrode, and the fourth conductive layer comprises a second branch of the initial signal line;
the second connection electrode is configured to connect the gate of the drive transistor and a second region of the first reset transistor through a via hole on an insulating layer, and the second branch of the initial signal line is connected to the first branch of the initial signal line through a via hole on an insulating layer; and
an orthographic projection of the second branch of the initial signal line on the substrate at least partially overlaps with an orthographic projection of the second connection electrode on the substrate.