US 12,288,516 B2
Display module and display device
Wenchao Bao, Beijing (CN); Yue Wu, Beijing (CN); Huihui Li, Beijing (CN); Miao Liu, Beijing (CN); Cheng Xu, Beijing (CN); and Jingbo Xu, Beijing (CN)
Assigned to Hefei BOE Joint Technology Co., Ltd., Anhui (CN); and BOE TECHNOLOGY GROUP CO., LTD., Beijing (CN)
Appl. No. 18/257,385
Filed by Hefei BOE Joint Technology Co., Ltd., Anhui (CN); and BOE TECHNOLOGY GROUP CO., LTD., Beijing (CN)
PCT Filed Jun. 24, 2022, PCT No. PCT/CN2022/101281
§ 371(c)(1), (2) Date Jun. 14, 2023,
PCT Pub. No. WO2023/245663, PCT Pub. Date Dec. 28, 2023.
Prior Publication US 2024/0321195 A1, Sep. 26, 2024
Int. Cl. G09G 3/3225 (2016.01); G02F 1/1345 (2006.01); G09G 3/32 (2016.01); G09G 3/36 (2006.01); H10K 59/126 (2023.01); H10K 59/131 (2023.01)
CPC G09G 3/3225 (2013.01) [G02F 1/13452 (2013.01); G09G 3/32 (2013.01); G09G 3/3648 (2013.01); H10K 59/126 (2023.02); H10K 59/131 (2023.02); G09G 2300/0426 (2013.01); G09G 2310/0291 (2013.01); G09G 2320/0219 (2013.01); G09G 2370/14 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A display module, comprising:
a display panel;
at least one bonding circuit board, each including first differential lines, wherein a first differential line includes a P-polarity differential sub-line and an N-polarity differential sub-line;
a plurality of chip-on-films, wherein an end of a chip-on-film is connected to the first differential line, and an other end of the chip-on-film is connected to the display panel; and
a plurality of buffer devices, arranged on the bonding circuit board, wherein a buffer device is connected to ends, proximate to the chip-on-film, of the P-polarity differential sub-line and the N-polarity differential sub-line, and the buffer device is configured to reduce signal reflection between the first differential line and the chip-on-film; wherein
the chip-on-film includes a low-voltage differential signaling (LVDS) interface circuit, the LVDS interface circuit includes a first signal receiving terminal, a second signal receiving terminal, a signal output terminal and a second resistor, wherein
the first signal receiving terminal is connected to the P-polarity differential sub-line, the second signal receiving terminal is connected to the N-polarity differential sub-line, and the signal output terminal is connected to the display panel; an end of the second resistor is connected to the first signal receiving terminal, and an other end of the second resistor is connected to the second signal receiving terminal.