| CPC G09G 3/2092 (2013.01) [G11C 19/184 (2013.01); G09G 2310/0286 (2013.01); G09G 2310/08 (2013.01); G11C 19/28 (2013.01)] | 18 Claims |

|
1. A gate driving unit, wherein an operating period of the gate driving unit comprises a first sub-period and a second sub-period, and the first sub-period and the second sub-period each comprise an input phase, an output phase, and a reset phase, the gate driving unit comprising:
a pull-up node control module electrically connected to a pull-up node, the pull-up node control module outputting an active level to the pull-up node during the input phase in response to a signal from a first pull-up control signal terminal;
a first pull-down node control module electrically connected to a first pull-down sub-node, wherein the first pull-down node control module configured to cause the first pull-down sub-node to be at an active level during at least a part of the reset phase in the first sub-period, and to cause the first pull-down sub-node to be at an inactive level during the reset phase in the second sub-period;
a second pull-down node control module electrically connected to a second pull-down sub-node, wherein the second pull-down node control module configured to cause the second pull-down sub-node to be at an inactive level during the reset phase in the first sub-period, and to cause the second pull-down sub-node to be at an active level during at least a part of the reset phase in the second sub-period; and
an output module electrically connected to an output terminal and a first clock signal terminal during the output phase in response to a signal from the pull-up node, electrically connected to the output terminal and a first level signal terminal during at least a part of the reset phase in the second sub-period in response to a signal from the first pull-down sub-node, and electrically connected to the output terminal and the first level signal terminal during at least a part of the reset phase in the first sub-period in response to a signal from the second pull-down sub-node, wherein the first clock signal terminal transmits a clock signal.
|