| CPC G06F 9/5027 (2013.01) [G06F 9/4893 (2013.01); G06F 9/5061 (2013.01); G06F 9/5094 (2013.01); G06F 11/3024 (2013.01); G06F 11/3058 (2013.01)] | 19 Claims |

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1. An apparatus comprising:
interface circuitry;
computer readable instructions; and
at least one processor circuit to be programmed based on the computer readable instructions to:
partition a plurality of cores of a microprocessor into subsets of cores including a first subset of cores and a second subset of cores;
access information that specifies a target lifespan of the microprocessor;
determine a threshold period of time based on the target lifespan, the threshold period of time less than the target lifespan; and
periodically switch at intervals of the threshold period of time between (i) a first state with the first subset of cores active and with the second subset of cores inactive, and (ii) a second state with the second subset of cores active and with the first subset of cores inactive.
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