US 12,288,072 B2
Methods, systems, and apparatuses for precise last branch record event logging
Jonathan Combs, Austin, TX (US); Michael Chynoweth, Placitas, NM (US); Beeman Strong, Portland, OR (US); Charlie Hewett, Bellevue, WA (US); Patrick Konsor, Hillsboro, OR (US); Vidisha Chirra, Austin, TX (US); Asavari Paranjape, Austin, TX (US); and Ahmad Yasin, Haifa (IL)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Mar. 27, 2021, as Appl. No. 17/214,823.
Prior Publication US 2022/0308882 A1, Sep. 29, 2022
Int. Cl. G06F 11/34 (2006.01); G06F 9/38 (2018.01); G06F 11/30 (2006.01); G06F 12/0802 (2016.01); G06F 17/40 (2006.01)
CPC G06F 9/3804 (2013.01) [G06F 11/3024 (2013.01); G06F 11/3495 (2013.01); G06F 12/0802 (2013.01); G06F 2212/30 (2013.01)] 24 Claims
OG exemplary drawing
 
1. An apparatus comprising:
an execution circuit to execute instructions;
a retirement circuit to retire executed instructions;
a status register; and
a last branch record circuit to:
in response to retirement by the retirement circuit of a first taken branch instruction, start a cycle timer and a performance monitoring event counter that is distinct from the cycle timer, and
in response to retirement by the retirement circuit of a second taken branch instruction, that is a next taken branch instruction in program order after the first taken branch instruction, write values from the cycle timer and the performance monitoring event counter into a first entry in the status register and clear the values from the cycle timer and the performance monitoring event counter.