US 12,288,071 B2
Register addressing information for data transfer instruction
Nigel John Stephens, Cambridge (GB); Jelena Milanovic, Sophia Antipolis (FR); and David Hennah Mansell, Cambridge (GB)
Assigned to Arm Limited, Cambridge (GB)
Appl. No. 18/006,806
Filed by ARM LIMITED, Cambridge (GB)
PCT Filed Jul. 5, 2021, PCT No. PCT/GB2021/051704
§ 371(c)(1), (2) Date Jan. 25, 2023,
PCT Pub. No. WO2022/023701, PCT Pub. Date Feb. 3, 2022.
Claims priority of application No. 2011874 (GB), filed on Jul. 30, 2020.
Prior Publication US 2023/0289186 A1, Sep. 14, 2023
Int. Cl. G06F 9/30 (2018.01)
CPC G06F 9/3016 (2013.01) [G06F 9/30036 (2013.01); G06F 9/30038 (2023.08); G06F 9/30105 (2013.01)] 19 Claims
OG exemplary drawing
 
1. An apparatus comprising:
instruction decoding circuitry configured to decode instructions;
register storage configured to store data; and
processing circuitry configured to perform data processing in response to an instruction decoded by the instruction decoding circuitry, to generate a processing result to be written to at least one register of the register storage; in which:
in response to a data transfer instruction specifying register addressing information for identifying a target portion of the register storage, the instruction decoding circuitry is configured to control the processing circuitry to perform a data transfer operation to transfer data to or from the target portion of the register storage; and
the register addressing information includes at least:
a base register identifier identifying a base register of the register storage for storing a base value; and
an immediate value specified in an encoding of the data transfer instruction, the immediate value representing a value to be added to the base value to provide an index value for selecting the target portion of the register storage.