US 12,288,069 B2
Stream data unit with multiple head registers
Joseph Zbiciak, San Jose, CA (US)
Assigned to Texas Instruments Incorporated, Dallas, TX (US)
Filed by TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed on Mar. 18, 2024, as Appl. No. 18/607,703.
Application 18/607,703 is a continuation of application No. 17/557,712, filed on Dec. 21, 2021, granted, now 11,934,833.
Application 17/557,712 is a continuation of application No. 16/458,756, filed on Jul. 1, 2019, granted, now 11,210,097, issued on Dec. 28, 2021.
Application 16/458,756 is a continuation of application No. 15/205,246, filed on Jul. 8, 2016, abandoned.
Prior Publication US 2024/0220258 A1, Jul. 4, 2024
Int. Cl. G06F 9/30 (2018.01); G06F 9/345 (2018.01); G06F 9/38 (2018.01); G06F 12/0875 (2016.01)
CPC G06F 9/30149 (2013.01) [G06F 9/30036 (2013.01); G06F 9/30038 (2023.08); G06F 9/30047 (2013.01); G06F 9/30065 (2013.01); G06F 9/3016 (2013.01); G06F 9/345 (2013.01); G06F 9/3824 (2013.01); G06F 9/383 (2013.01); G06F 12/0875 (2013.01); G06F 2212/452 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A device comprising:
a processor core;
a cache memory configured to store a set of data; and
a circuit coupled between the processor core and the cache memory, wherein the circuit includes:
an interface coupled to the cache memory and configured to receive the set of data from the cache memory;
a first buffer configured to store a first subset of the set of data; and
a second buffer configured to store a second subset of the set of data;
wherein the circuit is configured to provide at least one of the first subset of the set of data or the second subset of the set of data to the processor core based on an instruction that specifies whether to provide the first subset of the set of data from the first buffer, the second subset of the set of data from the second buffer, or both the first subset of the set of data from the first buffer and the second subset of the set of data from the second buffer.