| CPC G06F 9/3012 (2013.01) [G06F 9/30036 (2013.01); G06F 9/30145 (2013.01); G06F 9/384 (2013.01); G06F 9/3885 (2013.01)] | 25 Claims |
|
1. A processor comprising:
a register file comprising a plurality of registers organized into at least two register sets, each register set comprising a subset of the plurality of registers;
a plurality of functional units coupled to at least one register set;
an instruction issue unit receiving a first instruction, and issuing the first instruction if registers referenced by the first instruction are in one of the two register sets and the first instruction is assigned to be executed by a functional unit associated with the register set referenced by the first instruction;
an execution queue coupled to the instruction issue unit to receive the first instruction from the instruction issue unit, and dispatch the first instruction to the functional unit associated with the register set referenced by the first instruction; and
a register renaming unit that renames a destination register of the first instruction to a register in a register set corresponding to the register set of a source register for the first instruction, wherein the register renaming unit renames destination registers of instructions in an iteration of a loop to a first register set of the register file and renames the destination registers of instructions in another iteration of the loop to another register set of the register file.
|