US 12,288,064 B2
Hardware-based message block padding for hash algorithms
Manoj Kumar, Yorktown Heights, NY (US); Silvia Melitta Mueller, St. Ingbert (DE); Debapriya Chatterjee, Austin, TX (US); Niels Fricke, Herrenberg (DE); and Martijn Diede Berkers, Boeblingen (DE)
Assigned to INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US)
Filed by International Business Machines Corporation, Armonk, NY (US)
Filed on Aug. 10, 2022, as Appl. No. 17/884,739.
Prior Publication US 2024/0053989 A1, Feb. 15, 2024
Int. Cl. G06F 9/30 (2018.01); G06F 9/38 (2018.01); G09C 1/00 (2006.01); H04L 9/06 (2006.01)
CPC G06F 9/30101 (2013.01) [G06F 9/3802 (2013.01); H04L 9/0643 (2013.01); G09C 1/00 (2013.01); H04L 2209/12 (2013.01); H04L 2209/20 (2013.01)] 20 Claims
OG exemplary drawing
 
13. A method of data processing in a processor including a register file, said method comprising:
fetching, by an instruction fetch unit of the processor, instructions to be executed by the processor, wherein the instructions include a message padding instruction including an operand field indicating one of the plurality of registers buffering a message block segment of a message block to be padded and a mode field indicating which one of a plurality of different hash functions is to be applied to the message block; and
based on receiving the message padding instruction, an execution unit of the processor executing the message padding instruction, wherein executing the message padding instruction includes:
receiving, from the register file, the message block segment from one of the plurality of registers indicated by the operand field of the message padding instruction, wherein the message block spans multiple registers in the register file;
based on which one of the plurality of different hash functions is indicated by the mode field of the message padding instruction, determining whether at least one padding byte is to be inserted within the message block segment;
based on determining that the at least one padding byte is to be inserted within the message block segment, selecting a byte location among multiple byte locations in the message block segment at which to insert the at least one padding byte based on which one of the plurality of different hash function is indicated by the mode field and inserting the at least one padding byte at the selected byte location within the message block segment, wherein:
the selecting includes generating by an enable circuit an enable vector specifying the byte location; and
the inserting includes merging by an OR circuit, coupled to receive the enable vector and the message block segment, the at least one padding byte and the message block vector;
based on determining that the at least one padding byte is not to be inserted within the message block segment, refraining from inserting any padding byte within the message block segment; and
writing the message block segment as processed by the padding circuit back to the register file.