US 12,288,020 B2
Integrated circuit design and layout with multiple interpreters
Chia-Hsuan Cheng, Hsinchu (TW); Yao-Jih Hung, Hsinchu (TW); and Chi-Liang Yang, Taichung (TW)
Assigned to Synopsys, Inc., Sunnyvale, CA (US)
Filed by Synopsys, Inc., Mountain View, CA (US)
Filed on Jun. 8, 2022, as Appl. No. 17/835,822.
Claims priority of provisional application 63/208,940, filed on Jun. 9, 2021.
Prior Publication US 2022/0398370 A1, Dec. 15, 2022
Int. Cl. G06F 30/392 (2020.01); G06F 30/31 (2020.01)
CPC G06F 30/392 (2020.01) [G06F 30/31 (2020.01)] 20 Claims
OG exemplary drawing
 
1. A method for generating a circuit layout, the method comprising:
generating (i) a first symbol that indicates a first version and (ii) a second symbol that indicates a second version;
loading the first symbol and the second symbol into a design platform having a first evaluator for the first version and a second evaluator for the second version;
initializing a first interpreter of the first evaluator using the first symbol based on the first symbol indicating the first version and the second symbol indicating the second version; and
generating the circuit layout using the first interpreter.