US 12,288,017 B2
Simulation method for characteristics of transistor, simulation method for characteristics of electronic circuit including transistor, and nontransitory recording medium that stores simulation program for characteristics of transistor
Genshiro Kawachi, Kanagawa (JP)
Assigned to Wuhan Tianma Micro-Electronics Co., Ltd., Wuhan (CN)
Filed by Wuhan Tianma Micro-Electronics Co., Ltd., Wuhan (CN)
Filed on Jan. 21, 2021, as Appl. No. 17/153,943.
Claims priority of application No. 2020-009620 (JP), filed on Jan. 24, 2020.
Prior Publication US 2021/0232746 A1, Jul. 29, 2021
Int. Cl. G06F 30/36 (2020.01); G06F 30/3312 (2020.01); G06F 30/367 (2020.01); G06F 30/396 (2020.01); G06F 117/04 (2020.01); G06F 119/06 (2020.01); G06F 119/12 (2020.01)
CPC G06F 30/367 (2020.01) [G06F 30/3312 (2020.01); G06F 30/396 (2020.01); G06F 2101/10 (2013.01); G06F 2101/14 (2013.01); G06F 2117/04 (2020.01); G06F 2119/06 (2020.01); G06F 2119/12 (2020.01)] 7 Claims
OG exemplary drawing
 
1. A design method for characteristics of a pixel circuit of a display device through simulation,
the pixel circuit including at least a light emitting element and a transistor that controls a current flowing in the light emitting element,
the transistor including a semiconductor layer that includes a source and a drain that are separated from each other and a channel positioned between the source and the drain, and a gate electrode facing the channel of the semiconductor layer,
wherein a model parameter predetermined at least based on a measured result of the transistor is set by an input device,
wherein, the input device is caused to set a mathematical model equation including
a process (a) of calculating a thermal equilibrium trap charge density Q′T, based on the Poisson's equation expressing a relationship between an electrostatic potential inside the channel and charges including free carrier charges and trapped charges trapped in trapping states in the channel, and on the law of charge neutrality applied to charges accumulated on the gate electrode and the channel;
a process (b) of calculating a transient trap charge density qT after applying a voltage between the gate electrode and the semiconductor layer, in which assuming that a time variance of the transient trap charge density qT is expressed by a function obtained by superimposing multiple exponential functions having mutually different time constants;
a process (c) of calculating a free carrier charge density qI, based on the transient trap charge density qT; and
a process (d) of calculating a drain current Id flowing between the source and the drain, based on the free carrier charge density qI, and
wherein the subprocesses below are set to the process (b) of the mathematical model equation:
a subprocess (b1) of determining n delay time constants τNQS1 to τNQSn corresponding to the time constants included in the exponential functions, and charge densities QT1 to QTn of partial charges constituting the trapped charges having the delay time constants τNQS1 to τNQSn, respectively, where n is an integer of 2 or greater, based on a probability distribution of the partial charges constituting the trapped charges, the probability variable of which is delay time constant corresponding time required for the partial charges constituting the trapped charge to be trapped in the trapping states, and
a subprocess (b2) of calculating the transient trap charge density qT based on the delay time constants τNQS1 to τNQSn of the trapped charges and the charge densities QT1 to QTn of the trapped charges, and
wherein the design method includes
simulating, by an analog electronic circuit simulator, a transient response characteristic of the current flowing in the transistor in the pixel circuit based on the mathematical model equation, and
displaying, by an output device, a result of the simulation of the analog electronic circuit simulator.